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atmel-46002b-se-m90e26-datasheet_110714 features metering features ? metering features fully in compliance with the requirements of iec62052-11, iec62053-21 and iec62053-23; applicable in class 1 or class 2 single-phase watt- hour meter or class 2 single-phase var-hour meter. ? accuracy of 0.1% for active energy and 0.2% for reacti ve energy over a dynamic range of 5000:1. ? temperature coefficient is 15 ppm/ (typical) for on-chip reference voltage ? single-point calibration over a dynamic range of 5000:1 for active energy; no cali- bration needed for reactive energy. ? energy meter constant doubling at low current to save ve rification time. ? electrical parameters measurement: less than 0.5% fiducial error for vrms, irms, mean active/ reactive/ apparent power, frequency, power factor and phase angle. ? forward/ reverse active/ reactive energy wit h independent energy registers. active/ reactive energy can be output by pulse or read through energy registers to adapt to different applications. ? programmable startup and no-load power threshold. ? dedicated adc and different gains for l line and n line current sampling circuits. current sampled over shunt resistor or current transformer (ct); voltage sampled over resistor divider network or potential transformer (pt). ? programmable l line and n line metering modes: anti-tampering mode (larger power), l line mode (fixed l line), l+n mode (applicable for sing le-phase three-wire system) and flexible mode (configure through register). ? programmable l line and n line power difference threshold in anti-tampering mode. other features ? 3.3v single power supply. operating volt age range: 2.8~3.6v. metering accuracy guaranteed within 3.0v~3.6v. 5v compatible for digital input. ? built-in hysteresis for power-on reset. ? selectable uart interface and spi interfac e (four-wire spi interface or simplified three-wire spi interface with fixed 24 cycles for all registers operation). ? parameter diagnosis function and programm able interrupt output of the irq inter- rupt signal and the warnout signal. ? programmable voltage sag detecti on and zero-crossing output. ? channel input range - voltage channel (when gain is '1'): 120 vrms~600mvrms. - l line current channel (when gain is '24'): 5 vrms~25mvrms. - n line current channel (when gain is '1'): 120 vrms~600mvrms. ? programmable l line current gain: 1, 4, 8, 16, 24; programmable n line gain: 1, 2, 4. ? support l line and n line offset compensation. ? cf1 and cf2 output active and reactive energy pulses respectively which can be used for calibration or energy accumulation. ? crystal oscillator fr equency: 8.192 mhz. atmel m90e26 single-phase high-per formance wide-span energy metering ic datasheet
2 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 ? green ssop28 package. ? operating temperature: -40 ~ +85 . application the m90e26 is used for active and reactive energy metering for single-phase two-wire (1p2w), single-phase three-wire (1p3w) or anti-tampering energy meters. with the measuremen t function, the m90e26 can also be used in power instru- ments which need to measure voltage, current, etc. description the m90e26 is a high-performance wide-span energy metering chip. the adc and dsp technology ensure the chip's long- term stability over variati ons in grid and ambient environmental conditions. block diagram figure-1 m90e26 block diagram reference voltage power on reset crystal oscillator spi / uart vref i1p i1n vp vn l line forward/reverse active/ reactive power l line apparent power l line irms vrms i2p i2n mmd1 mmd0 cs sclk sdo/ ut x sdi/ ur x osci osco reset adc adc hpf1 hpf0 dsp module pga x1/x4/x8/ x16/x24 adc active energy pulse output reactive energy pulse output cf1 cf2 hpf1 hpf0 hpf1 hpf0 n line forward/reverse active/ reactive power n line apparent power n line irms power factor/ angle/frequency warnout/irq/zx zx irq warnout ngain
3 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 features................. ................ ................. .............. .............. .............. .............. ............. ............... ......... 1 application .............. ................. ................ .............. .............. .............. .............. ............. ...................... 2 description .............. ................. ................ .............. .............. .............. .............. ............. ...................... 2 block diagram................ ................. ................ ................ ................. ................ ................ ................... 2 1 pin assignment ............. ................ ................. ................ ................ ................. ................ ............... 7 2 pin description .............. ................ ................. ................ ................ ................. .............. ................. 8 3 functional description ........ ................ ................. ................ ................. ................ ............. ......... 10 3.1 dynamic metering range .............. ................ .............. .............. ............... .............. .............. ... 10 3.2 startup and no-load power .. ............... ................ ................. ................ ................. ............... .. 10 3.3 energy registers ........ ................. ................ ................ ................. ................ ................. .......... 11 3.4 n line metering and anti-tampering ................ ................ ................. .............. .............. .......... 12 3.4.1 metering mode and l/n line current sampling gain configuration ........................................... 12 3.4.2 anti-tampering mode ...................................................................................................... ............ 12 3.5 measurement and zero-crossing ....... ................ ................ ............... .............. .............. .......... 13 3.5.1 measurement .............................................................................................................. ................. 13 3.5.2 zero-crossing ............................................................................................................ .................. 13 3.6 calibration ............... ................ ................ ................. ................ ................. ............... ................ 14 3.7 reset ................ ................ ................ .............. .............. .............. ............... ............. .................. 14 4 interface ............. ................. ................ .............. .............. .............. .............. .............. ............ ........ 15 4.1 spi interface ...... ................ ................. ................ .............. .............. .............. ............. .............. 15 4.1.1 four-wire mode ........................................................................................................... ................ 15 4.1.2 three-wire mode .......................................................................................................... ............... 16 4.1.3 timeout and protection ................................................................................................... ............ 17 4.2 uart interface ........... ................. ................ ................ ................. ................ ................ ........... 18 4.2.1 byte level timing ........................................................................................................ ................ 18 4.2.2 write transaction ........................................................................................................ ................ 18 4.2.3 read transaction ......................................................................................................... ................ 19 4.2.4 checksum ................................................................................................................. ................... 19 4.3 warnout pin for fatal error warning ................ ................ .............. .............. .............. ............. 2 0 4.4 low cost implementat ion in isolation with mcu ... .............. ............... .............. .............. .......... 20 5 register .............. ................. ................ .............. .............. .............. .............. .............. .................... 21 5.1 register list ............ ................ ................ ................. ................ ................. ................ ............... 21 5.2 status and special register ......... ................ ................ .............. ............... .............. ............ ..... 22 5.3 metering/ measurement calibration and configuration ...... ............... .............. .............. .......... 26 5.3.1 metering calibration and configuration register ......................................................................... 26 5.3.2 measurement calibration register ......................................................................................... ..... 34 5.4 energy register .......... ................. ................ ................ ................. ................ ................ ........... 39 5.5 measurement register ..... ................ ................. ................ ................. ................ ................ ...... 44 table of contents
4 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 6 electrical specification ............... ................ .............. .............. ............... .............. ............. ........... 51 6.1 electrical specification ................. ................ ................ ................. ................ ................. .......... 51 6.2 spi interface timing ...... ................ ................ ................. ................ ................. ............... ......... 53 6.3 power on reset timing ............ ................. ................ ................ ............... .............. ............ ..... 54 6.4 zero-crossing timing ...... ................ ................. ................ ................. ................ ............... ....... 55 6.5 voltage sag timing ........ ................ ................ ................. ................ ................. ............... ......... 55 6.6 pulse output ............. ................ ................. ................ ................ ................. ................ ............. 56 6.7 absolute maximum rating . ................. ................ ................ ................. ................ ................. ... 56 ordering information.......... ................ ................. ................ ................ ................. ............... ............. 57 packaging drawings........... ................ ................. ................ ................ ................. ................ ............ 58 revision history .............. ................ ................ ................. ................ ................. .............. ................ 59
5 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 table-1 pin description ...................................................................................................... ............................................... 8 table-2 active energy metering error ......................................................................................... .................................... 10 table-3 reactive energy metering error ....................................................................................... .................................. 10 table-4 threshold configuration fo r startup and no-load power ................................................................ .................. 10 table-5 energy registers ..................................................................................................... .......................................... 11 table-6 metering mode ........................................................................................................ ........................................... 12 table-7 the measurement format ............................................................................................... .................................. 13 table-8 read / write result in four-wire mode ................................................................................ ............................. 17 table-9 read / write result in three-wire mode ............................................................................... ............................ 17 table-10 register list ....................................................................................................... ................................................ 21 table-11 spi timing specification ............................................................................................ ........................................ 53 table-12 power on reset specification ........... ............................................................................. ................................... 54 table-13 zero-crossing specification ......................................................................................... ...................................... 55 table-14 voltage sag specification ........................................................................................... ....................................... 56 list of tables
6 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 figure-1 m90e26 block diagram ................................................................................................ ....................................... 2 figure-2 pin assignment (top view) ................ ........................................................................... ....................................... 7 figure-3 read sequence in four-wire mode ..... ................................................................................ ............................. 15 figure-4 write sequence in f our-wire mode .................................................................................... ............................... 15 figure-5 read sequence in thre e-wire mode .................................................................................... ............................ 16 figure-6 write sequence in thr ee-wire mode ................................................................................... .............................. 16 figure-7 uart byte level timi ng .............................................................................................. ...................................... 18 figure-8 write transaction ................................................................................................... ............................................ 18 figure-9 read transaction .. .................................................................................................. ........................................... 19 figure-10 4-wire spi timing diagram .............. ............................................................................ .................................... 53 figure-11 3-wire spi timing diagram .............. ............................................................................ .................................... 53 figure-12 power on reset timing diagram ...................................................................................... ............................... 54 figure-13 zero-crossing timing diagram ....................................................................................... .................................. 55 figure-14 voltage sag timing diagram ............ ............................................................................. ................................... 55 figure-15 output pulse width ................................................................................................. .......................................... 56 list of figures
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 7 1 pin assignment figure-2 pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 reset dvdd avdd agnd i1p i1n i2p i2n vp vn vref agnd resv_low warnout cs sclk sdo/utx sdi/urx dgnd mmd1 mmd0 osci osco usel cf1 cf2 zx irq
8 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 2 pin description table-1 pin description name pin no. i/o note 1 type description reset 4ilvttl reset : reset pin (active low) this pin should connect to ground through a 0.1 f filter capacitor. in appli- cation it can also directly connect to one output pin from microcontroller (mcu). dvdd 3 i power dvdd: digital power supply this pin provides power supply to t he digital part. it should be decoupled with a 10 f electrolytic capacitor and a 0.1 f capacitor. dgnd 2 i power dgnd: digital ground avdd 5 i power avdd: analog power supply this pin provides power supply to the analog part. it should be decoupled with a 0.1 f capacitor. vref 13 o analog vref: output pin for reference voltage this pin should be decoupled with a 1 f capacitor and a 1nf capacitor. agnd 6, 14 i power agnd: analog ground i1p i1n 10 11 i analog i1p: positive inpu t for l line current i1n: negative input for l line current these pins are differential inputs for l line current. input range is 5 vrms ~ 25mvrms when gain is '24'. i2p i2n 7 8 i analog i2p: positive input for n line current i2n: negative input for n line current these pins are differential inputs for n line current. input range is 120 vrms ~ 600mvrms when gain is '1'. vp vn 16 15 i analog vp: positive input for voltage vn: negative input for voltage these pins are differential in puts for voltage. input range is 120 vrms ~ 600mvrms. usel 12 i lvttl usel: uart/spi inte rface selection high: uart interface low: spi interface note: this pin should not change after reset. cs 24 i lvttl cs : chip select (active low) of spi in 4-wire spi mode, this pin must be driven from high to low for each read/ write operation, and maintain low for the entire operation. in 3-wire spi mode, this pin must be low all the time. refer to section 4.1 . in uart interface, this pin should be connected to vdd. sclk 25 i lvttl sclk: serial clock of spi this pin is used as the clock for the spi interface. data on sdi is shifted into the chip on the rising edge of sclk while data on sdo is shifted out of the chip on the falling edge of sclk. in uart interface, this pin should be connected to ground.
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 9 sdo/utx 26 oz lvttl sdo: serial data output of spi this pin is used as the data output for the spi interface. data on this pin is shifted out of the chip on the falling edge of sclk. utx: uart data transmit this pin is used to transmit data for the uart interface. this pin needs to be pulled up to vdd by a 10k resistor.? note : uart and spi interface is selected by the usel pin. sdi/urx 27 i lvttl sdi: serial data input of spi this pin is used as the data input for the spi interface. address and data on this pin is shifted into the chip on the rising edge of sclk. urx: uart data receive this pin is used to receive data for the uart interface. note : uart and spi interface is selected by the usel pin. mmd1 mmd0 1 28 ilvttl mmd1/0: metering mo de configuration 00: anti-tampering mode (larger power); 01: l line mode (fixed l line); 10: l+n mode (applicable for si ngle-phase three-wire system); 11: flexible mode (line specified by the lnsel bit ( mmode , 2bh)) osci 22 i lvttl osci: external crystal input an 8.192 mhz crystal is connected between osci and osco. in applica- tion, this pin should be connected to ground through a 12pf capacitor. osco 23 o lvttl osco: external crystal output an 8.192 mhz crystal is connected between osci and osco. in applica- tion, this pin should be connected to ground through a 12pf capacitor. cf1 cf2 18 19 olvttl cf1: active energy pulse output cf2: reactive energy pulse output these pins output active/reactive energy pulses. zx 21 o lvttl zx: voltage zero-crossing output this pin is asserted when voltage crosses zero. zero-crossing mode can be configured to positive zero-crossing, negative zero-crossing or all zero- crossing by the zxcon[1:0] bits ( mmode , 2bh). irq 20 o lvttl irq: interrupt output this pin is asserted when one or more events in the sysstatus register (01h) occur. it is deasserted when there is no bit set in the sysstatus regis- ter (01h). warnout 17 o lvttl warnout: fatal error warning this pin is asserted when there is metering parameter calibration error or voltage sag. refer to section 4.3 . resv_low 9 i lvttl reserved for normal operation, these pins should be connected to ground. table-1 pin descrip tion (continued) name pin no. i/o note 1 type description
10 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 3 functional description 3.1 dynamic metering range accuracy is 0.1% for active energy metering and 0.2% for re active energy metering over a dynamic range of 5000:1 (typi- cal). refer to ta b l e - 2 and table-3 . 3.2 startup and no-load power startup and no-load power thresholds are programmable, both for active and reactive power. the related registers are listed in ta b l e - 4 . the m90e26 will start within 1.2 times of the theoretical startup time of the configured star tup power, if startup power is les s than the corresponding power of 20ma when power factor or sin is 1.0. the m90e26 has no-load status bits, t he pnoload/qnoload bit (enstatus, 46h) . the m90e26 will not output any active pulse (cf1) in active no-load state. the m90e26 will not output any reactive pu lse (cf2) in reactive no-load state. table-2 active energy metering error current power factor error (%) 20ma i 50ma 1.0 0.2 50ma i 100a 0.1 50ma i 100ma 0.5 (inductive) 0.8 (capacitive) 0.2 100ma i 100a 0.1 note: shunt resistor is 250 ? or ct ratio is 1000:1 and load resistor is 6 . table-3 reactive energy metering error current sin (inductive or capacitive) error ( % ) 20ma i 50ma 1.0 0.4 50ma i 100a 0.2 50ma i 100ma 0.5 0.4 100ma i 100a 0.2 note: shunt resistor is 250 ? or ct ratio is 1000:1 and load resistor is 6 . table-4 threshold configuration for startup and no-load power threshold register threshold for acti ve startup power pstartth , 27h threshold for active no-load power pnolth , 28h threshold for reactive startup power qstartth , 29h threshold for reactive no-load power qnolth , 2ah
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 11 3.3 energy registers the m90e26 provides energy pulse output cfx (cf1/cf2) which is proportionate to active/reactive energy. energy is usu- ally accumulated by adding the cfx pulses in system applicat ions. alternatively, the m90e26 provides energy registers. there are forward (inductive), reverse (capacitive) and absolute energy registers for both active and reactive energy. refer to table-5 . each energy register is cleared after read. the resolution of energy registers is 0.1cf, i.e. one lsb represents 0.1 energy pulse. table-5 energy registers energy register forward active energy apenergy , 40h reverse active energy anenergy , 41h absolute active energy atenergy , 42h forward (inductive) reactive energy rpenergy , 43h reverse (capacitive) reactive energy rnenergy , 44h absolute reactive energy rtenergy , 45h
12 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 3.4 n line metering and anti-tampering 3.4.1 metering mode and l/n line cu rrent sampling gain configuration the m90e26 has two current sampling circuits with n line metering and anti-tampering functions. the mmd1 and mmd0 pins are used to configure the metering mode. refer to table-6 . the m90e26 has two current sampling circuits with different gain configurations. l line gain can be 1, 4, 8, 16 and 24, and n line gain can be 1, 2 and 4. the configuration is made by the mmode register (2bh). generally l line can be sampled over shunt resistor or ct. n line can be sampled over ct for isolation consideration. note that rogowski coil is not sup- ported. 3.4.2 anti-tampering mode threshold in anti-tampering mode, the power difference threshold between l line and n line can be: 1%, 2%,... 12%, 12.5%, 6.25%, 3.125% and 1.5625%, altogether 16 choices. the configuratio n is made by the pt hresh[3:0] bits ( mmode , 2bh) and the default value is 3.125%. the threshold is applicable for active energy. the metering line of the reactive energy follows that of the active energy. compare method in anti-tampering mode, the compare method is as follows: if current metering line is l line and n line is switched as the metering line, ot herwise l line keeps as the metering line. if current metering line is n line and l line is switched as the metering line, otherwise n line keeps as the metering line. this method can achieve hysteresis around the threshold automatically. l line is employed after reset by default. special treatment at low power when power is low, general factors such as the quantization error or calibration difference between l line and n line might cause the power difference to be exceeded. to ensure l line and n line to start up normally, special treatment as follows is adopted: the line with higher power is selected as the metering line when both l line and n line power are lower than 8 times of the startup power but higher than the startup power. table-6 metering mode mmd1 mmd0 metering mode cfx (cf1 or cf2) output 0 0 anti-tampering mode (larger power) cfx represents the larger energy line. refer to sec- tion 3.4.2 . 0 1 l line mode (fixed l line) cfx represents l line energy all the time. 10 l+n mode (applicable for single-phase three-wire sys- tem) cfx represents the arithmetic sum of l line and n line energy 11 flexible mode (line spec ified by the lnsel bit ( mmode , 2bh)) cfx represents energy of the specified line. threshold 100% * power active line l power active line l - power active line n > >
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 13 3.5 measurement and zero-crossing 3.5.1 measurement the m90e26 has the following measurements: ? voltage rms ? current rms (l line/n line) ? mean active power (l line/n line) ? mean reactive power (l line/n line) ? voltage frequency ? power factor (l line/n line) ? phase angle between voltage and current (l line/n line) ? mean apparent power (l line/n line) the above measurements are all calculated with fiducial erro r except for frequency. the frequency accuracy is 0.01hz, and the other measurement accuracy is 0.5%. fiducial error is calculated as follow: where u mea is the measured voltage, u real is the actual voltage and u fv is the fiducial value. 3.5.2 zero-crossing the zx pin is asserted when the sampling voltage crosses zero . zero-crossing mode can be configured to positive zero- crossing, negative zero-crossing and all zero-crossing by the zxcon[1:0] bits ( mmode , 2bh). refer to section 6.4 . the zero-crossing signal can facilitate ope rations such as relay oper ation and power line carrier transmission in typical smart meter applications. table-7 the measurement format measurement fiducial value (fv) m90e26 defined format range comment voltage rms un xxx.xx 0~655.35v current rms note 1, note 2 imax as 4ib xx.xxx 0~65.535a active/ reactive power note 1 maximum power as un*4ib xx.xxx -32.768~+32.767 kw/kvar complement, msb as the sign bit apparent power note 1 un*4ib xx.xxx 0~+32.767 kva complement, msb always '0' frequency fn xx.xx 45.00~65.00 hz power factor note 3 1.000 x.xxx -1.000~+1.000 signed, msb as the sign bit phase angle note 4 180 xxx.x -180~+180 signed, msb as the sign bit note 1: all registers are of 16 bits. for cases when the current and ac tive/reactive/apparent power goes beyond the above range, it is suggested to be handled by microcontroller (m cu) in application. for exampl e, register value can be ca librated to 1/2 of the ac tual value during calibration, then multiply 2 in applic ation. note that if the actu al current is twice of that of the m90e26, the actual active/reactive/ apparent power is also twic e of that of the m90e26. note 2: the accuracy is not guaranteed when the current is lo wer than 15ma. note that th e tolerance is 25 ma at i fv of 5a and fiducial accuracy of 0.5%. note 3: power factor is obtained by active power dividing apparent power note 4: phase angle is obtained when voltage/current crosses zero at the frequency of 256khz. precision is not guaranteed at small current. 100% * u u - u rror fiducial_e fv real mea =
14 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 3.6 calibration calibration includes metering and measurement calibration. metering calibration the m90e26 design methodology guarantees the accuracy over the entire dynamic range, after metering calibration at one specific current, i.e. the basic current of i b . the calibration procedure includes the following steps: 1. calibrate gain at unity power factor; 2. calibrate phase angle compensation at 0.5 inductive power factor. generally, line curr ent sampling is suscept ible to the circuits around the sensor when shunt resistor is employed as the current sensor in l line. for example, the transformer in th e energy meter?s power supply may conduct interference to the shunt resistor. such interference will cause pe rceptible metering error, especially at low current conditio ns. the total inter- fere is at a statistically constant level. in this case, the m90e26 provides the power offset compensation feature to improve metering performance. l line and n line need to be calibrated sequentially. reactive energy does not need to be calibrated after active energy cali- bration completed. measurement calibration measurement calibration includes gain calibration for voltage rms and current rms. considering the possible nonlinearity around zero caused by external components, the m90e26 also provides offset compensation for voltage rms, current rms, mean active power and mean reactive power. the m90e26 design methodology guarantees automatic calibration for frequency, phase angle and power factor measure- ment. 3.7 reset the m90e26 has an on-chip power supply monitor circuit with built-in hysteresis. the m90e26 only works within the volt- age range. the m90e26 has three means of reset: power-on reset, hardware reset and software reset. all registers resume to their default value after reset. power-on reset: power-on reset is initia ted during power-up. refer to section 6.3. hardware rese t: hardware reset is initiated when the reset pin is pulled low. the width of the reset signal should be over 200 s. software reset: soft ware reset is initia ted when ?789ah? is written to the software reset register ( softreset , 00h).
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 15 4 interface the m90e26 supports both serial peripheral interface (spi) and uart interface. the selection is made by the usel pin. when the usel pin is low, spi interface is selected. when the usel pin is high, uart interfac e is selected. note that the usel pin should not change after reset. 4.1 spi interface spi is a full-duplex, synchronous channel. there are two spi modes: four-wire mode and three-wire mode. in four-wire mode, four pins are used: cs , sclk, sdi and sdo. in three-wire mode, thre e pins are used: sclk, sdi and sdo. data on sdi is shifted into the chip on the rising edge of sclk while data on sdo is sh ifted out of the chip on the falling edge of sclk. the lastdata register (06h) stores the 16-bit data that is just read or written. 4.1.1 four-wire mode in four-wire mode, the cs pin must be driven low for the entire read or write operation. the first bit on sdi defines the access type and the lower 7-bit is decoded as address. read sequence as shown in figure-3 , a read operation is initiated by a high on sdi followed by a 7-bit register address. a 16-bit data in this register is then shifted out of the chip on sdo. a complete read operation contains 24 cycles. figure-3 read sequence in four-wire mode write sequence as shown in figure-4 , a write operation is initiated by a low on sdi followed by a 7-bit register address. a 16-bit data is then shifted into the chip on sdi. a comple te write operation contains 24 cycles. figure-4 write sequence in four-wire mode cs sclk sdi sdo 10 123456789 111213141516171819202122 24 a0 a6 a5 a4 a3 a2 a1 register address high impedance d15 don't care d0 16-bit data 23 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 cs sclk sdi sdo 10 123456789 11121314151617181920212223 a0 a6 a5 a4 a3 a2 a1 16-bit data high impedance d0 d7 d6 d5 d4 d3 d2 d1 register address d15 24 d14d13d12d11d10 d9 d8
16 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 4.1.2 three-wire mode in three-wire mode, cs is always at low level. when there is no operation, sclk keeps at high level. the start of a read or write operation is triggered if sclk is consistently low for at least 400 s. the subsequent read or write operation is similar to that in four-wire mode. refer to figure-5 and figure-6 . figure-5 read sequence in three-wire mode figure-6 write sequence in three-wire mode cs sclk 10 123456789 11121314151617181920212223 register address 24 1234 low 400 s drive low sdi sdo a0 a6 a5 a4 a3 a2 a1 hign impedance d 15 don't care 16-bit data d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 don t care a6 a5 a4 high impedance low 400 s cs sclk sdi sdo 10 123456789 11121314151617181920212223 a0 a6 a5 a4 a3 a2 a1 16-bit data high impedance d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 register address d 14 d 15 24 d 13 d 12 d 11 d 10 d 9 d 8 1234 a6 a5 a4 don't care drive low low 400 s low 400 s don't care
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 17 4.1.3 timeout and protection timeout occurs if sclk does not toggle for 6ms in both four-wire and three-wire modes. when timeout, the read or write operation is aborted. if there are more than 24 sclk cycles when cs is driven low in four-wire mode or between two starts in three-wire mode, writing operation is prohibited while normal reading operation can be completed by taking the first 24 sclk cycles as the valid ones. however, the reading result might not be the intended one. a read access to an invalid address returns all zero. a write access to an invalid address is discarded. ta b l e - 8 and ta b l e - 9 list the read or write result in different conditions. table-8 read / write result in four-wire mode condition result operation timeout sclk cycles note 1 read/write status lastdata register update read - note 2 >=24 normal read yes - note 2 <24 partial read no write no =24 normal write yes no !=24 no write no yes - no write no note 1: the number of sclk cycles when cs is driven low or the number of sc lk cycles before timeout if any. note 2: '-' stands for don't care. table-9 read / write result in three-wire mode condition result operation timeout sclk cycles note 1 read/write status lastdata register update read no >=24 note 2 normal read yes timeout after 24 cycles >24 normal read yes timeout before 24 cycles - note 3 partial read no timeout at 24 cycles =24 normal read yes write no =24 normal write yes no !=24 no write no yes - no write no note 1: the number of sclk cycles between 2 starts or the number of sclk cycles before timeout if any. note 2: there is no such case of less than 24 sclk cycles when there is no timeout in three-wire mode, becau se the first few sclk cycles in the next operati on is counted into this operation. in this case, da ta is corrupted. note 3: '-' stands for don't care.
18 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 4.2 uart interface the uart interface is of 8-bit data onl y, with no parity checking features. a read/write transaction is composed of 6 bytes? transfer, starti ng always from the host transm itting the first byte ?feh?. the second byte is referenced as rw _address, which has a r/w bit (bit 7) and 7 address bits (bit6-0). upon receiving commands from the host, the m90e26 will send data and/or checksum bytes back to the host within 5ms if the checksum is confirmed to be correct. interval between successive uart bytes from the m90e26 is 5 bits maximum. the m90e26 will time out the current transa ction if the host byte interval (idlin g time between two successive bytes) is greater than 20ms. once tran saction timeout or checksum failure, the m90e26 will abort t he current transaction and wait for the starting byte ?feh? of the new transaction and ignore other data that received. the host needs to have a timeout scheme to detect transaction failure. in addition, host needs to wait at least 20ms to start a new transaction to allow the m90e26 to recover from a failure condition. uart baud rate is determined by the host, and it can be aut o-detected by the m90e26. the baud rates supported are 2400 and 9600. the first byte (feh) is used in detecting the baud-rate. the baud-rate of a transaction shall be kept unchanged. for a new transaction, host may change the baud rate. however, it is suggested that boad rate remain the same in applica- tion. the 8-bit data in tx/rx pin is shifted in a lsb (bit0) first manner. 4.2.1 byte level timing the timing for each byte is as shown in figure-7 . figure-7 uart byte level timing 4.2.2 write transaction a complete write transaction is composed of six bytes, fi ve from the host and one from the m90e26 as shown in figure-8 . figure-8 write transaction utx/ urx bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit data frame idle tx io drive high impedence tx io drive note: the utx pin will be in high impedance state when not transmitting w (0) address data_lsb data_msb chksum addr+data chksum addr+data host (urx) m90e26 (utx) 0xfe byte interval max 20 ms response time max 5 ms
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 19 4.2.3 read transaction a complete read transaction is composed of six bytes, three from the host and three from the m90e26 as shown in figure- 9 . figure-9 read transaction 4.2.4 checksum checksum is done by adding the bytes as unsigned numbers, dropping the overflow bits, and taking the result as the checksum. checksum is calculated with address, data or addr ess+data, depending on the transaction type: write transaction: host checksum = rw_address+data_msb+data_lsb m90e26 checksum = rw_address+data_msb+data_lsb read transaction: host checksum = rw_address m90e26 checksum = data_msb + data_lsb host (urx) m90e26 (utx) r (1) address 0xfe chksum address data_lsb data_msb chksum data byte interval max 20 ms byte interval max 5 bits response time max 5 ms
20 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 4.3 warnout pin for fatal error warning fatal error warning is raised through the warnout pin in two cases: checksum calibration error and voltage sag. calibration error the m90e26 performs diagnosis on a regular basis for importan t parameters such as calibration parameters and metering configuration. when checksum is no t correct, the calerr[1:0] bits ( sysstatus , 01h) are set, and both the warnout pin and the irq pin are asserted. when checksum is not correct, the metering part does not work to prevent a large number of pulses during power-on or any abnormal situation upon incorrect parameters. voltage sag voltage sag is detected when voltage is continuously below the voltage sag threshold for one cycle which starts from any zero-crossing point. voltage threshold is configured by the sagth register (03h). refer to section 6.5 . when voltage sag occurs, the sagwarn bit ( sysstatus , 01h) is set and the warnout pin is asserted if the funcen register (02h) enables voltage sag warning through the warnout pin. th is function helps reduce power-down detection circuit in system design. in addition, the method of judging voltage sag by detecting ac side voltage eliminates the influence of large capacitor in traditional rectifier circuit, and can detect voltage sag earlier. 4.4 low cost implementation in isolation with mcu the following functions can be achieved at low cost when the m90e26 is isolated from the mcu: spi/uart: mcu can perform read and writ e operations through low speed optocoupler (e.g. ps2501) when the m90e26 is isolated from the mcu. for the spi interface, it can be either of 3-wire or 4-wire. energy pulses cfx: energy can be accumulated by reading va lues in corresponding energy registers. cfx can also con- nect to the optocoupler and the energy pulse light can be turned on by cfx. fatal error warnout: fatal error can be acquired by reading the calerr[1:0] bits ( sysstatus , 01h). irq: irq interrupt can be acquired by reading the sysstatus register (01h). reset: the m90e26 is reset when ?789ah? is written to the software reset register ( softreset , 00h).
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 21 5register 5.1 register list table-10 register list register address register name read/write type functional description page status and special register 00h softreset w software reset p22 01h sysstatus r/c system status p23 02h funcen r/w function enable p24 03h sagth r/w voltage sag threshold p24 04h smallpmod r/w small-power mode p25 06h lastdata r last read/write spi/uart value p25 metering calibration and configuration register 08h lsb r/w rms/power 16-bit lsb p26 20h calstart r/w calibration start command p26 21h plconsth r/w high word of pl_constant p27 22h plconstl r/w low word of pl_constant p27 23h lgain r/w l line calibration gain p28 24h lphi r/w l line calibration angle p28 25h ngain r/w n line calibration gain p28 26h nphi r/w n line calibration angle p29 27h pstartth r/w active startup power threshold p29 28h pnolth r/w active no-load power threshold p29 29h qstartth r/w reactive startup power threshold p30 2ah qnolth r/w reactive no-load power threshold p30 2bh mmode r/w metering mode configuration p31 2ch cs1 r/w checksum 1 p33 measurement calibration register 30h adjstart r/w measurement calibration start command p34 31h ugain r/w voltage rms gain p34 32h igainl r/w l line current rms gain p35 33h igainn r/w n line current rms gain p35 34h uoffset r/w voltage offset p35 35h ioffsetl r/w l line current offset p36 36h ioffsetn r/w n line current offset p36 37h poffsetl r/w l line active power offset p36 38h qoffsetl r/w l line reactive power offset p37 39h poffsetn r/w n line active power offset p37 3ah qoffsetn r/w n line reactive power offset p37 3bh cs2 r/w checksum 2 p38 energy register 40h apenergy r/c forward active energy p39 41h anenergy r/c reverse active energy p40 42h atenergy r/c absolute active energy p40 43h rpenergy r/c forward (inductive) reactive energy p41
22 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 5.2 status and special register softreset software reset 44h rnenergy r/c reverse (capacitive) reactive energy p41 45h rtenergy r/c absolute reactive energy p42 46h enstatus r metering status p43 measurement register 48h irms r l line current rms p44 49h urms r voltage rms p44 4ah pmean r l line mean active power p45 4bh qmean r l line mean reactive power p45 4ch freq r voltage frequency p46 4dh powerf r l line power factor p46 4eh pangle r phase angle between voltage and l line current p47 4fh smean r l line mean apparent power p47 68h irms2 r n line current rms p48 6ah pmean2 r n line mean active power p48 6bh qmean2 r n line mean reactive power p49 6dh powerf2 r n line power factor p49 6eh pangle2 r phase angle between voltage and n line current p50 6fh smean2 r n line mean apparent power p50 address: 00h type: write default value: 0000h bit name description 15 - 0 softreset[15:0] software reset register. the m90e26 resets if only 789ah is written to this register. table-10 register list (continued) register address register name read/write type functional description page 15 14 13 12 11 10 9 8 softreset15 softreset14 softreset13 softreset12 softreset11 softreset10 softreset9 softreset8 76543210 softreset7 softreset6 softrese t5 softreset4 softreset3 soft reset2 softreset1 softreset0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 23 sysstatus system status address: 01h type: read/clear default value: 0000h bit name description 15 - 14 calerr[1:0] these bits indicate cs1 checksum status. 00: cs1 checksum correct (default) 11: cs1 checksum error. at the same time, the warnout pin is asserted. 13 - 12 adjerr[1:0] these bits indicate cs2 checksum status. 00: cs2 checksum correct (default) 11: cs2 checksum error. 11 - 8 - reserved. 7 lnchange this bit indicates whether there is any chan ge of the metering line (l line and n line). 0: metering line no change (default) 1: metering line changed 6revqchq this bit indicates whether there is any c hange with the direction of reactive energy. 0: direction of reactive energy no change (default) 1: direction of reactive energy changed this status is enabled by the revqen bit( funcen , 02h). 5 revpchg this bit indicates whether there is any c hange with the direction of active energy. 0: direction of active energy no change (default) 1: direction of active energy changed this status is enabled by the revpen bit ( funcen , 02h). 4 - 2 - reserved. 1sagwarn this bit indicates th e voltage sag status. 0: no voltage sag (default) 1: voltage sag voltage sag is enabled by the sagen bit ( funcen , 02h). voltage sag status can also be reported by the warnout pin. it is enabled by the sagwo bit( funcen , 02h). 0- reserved. note: any of the above events will prompt the irq pin to be assert ed, which can be supplied to external mcu as an interrupt. 15 14 13 12 11 10 9 8 calerr1 calerr0 adjerr1 adjerr0 - - - - 76543210 lnchange revqchg revpchg - - - sagwarn -
24 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 funcen function enable sagth voltage sag threshold address: 02h type: read/write default value: 000ch bit name description 15 - 6 - reserved. 5 sagen this bit determines whether to enable the voltage sag interrupt. 0: disable (default) 1: enable 4sagwo this bit determines whether to enable voltage sag to be reported by the warnout pin. 0: disable (default) 1: enable 3revqen this bit determines whether to enable the dire ction change interrupt of reactive energy. 0: disable 1: enable (default) 2 revpen this bit determines whether to enable the direction change interrupt of active energy. 0: disable 1: enable (default) 1 - 0 - reserved. address: 03h type: read/write default value: 1d6ah bit name description 15 - 0 sagth[15:0] voltage sag threshold co nfiguration. data forma t is xxx.xx. unit is v. the power-on value of sagth is 1d6ah, which is calculated by 22000*sqrt(2)*0.78/(4*ugain/32768) for details, please refer to related application note 46102. 15 14 13 12 11 10 9 8 -------- 76543210 - - sagen sagwo revqen revpen - - 15 14 13 12 11 10 9 8 sagth15 sagth14 sagth13 sagth12 sagth11 sagth10 sagth9 sagth8 76543210 sagth7 sagth6 sagth5 sagth4 sagth3 sagth2 sagth1 sagth0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 25 smallpmod small-power mode lastdata last read/write spi/uart value address: 04h type: read/write default value: 0000h bit name description 15 - 0 smallpmod[15:0] small-power mode command. a987h: small-power mode. the relationship between t he register value of l line and n line active/reactive power in small-power mode and normal mode is: power in normal mode = power in small-power mode *igain*ugain /(100000 * 2^42) others: normal mode. small-power mode is mainly used in the power offset calibration. address: 06h type: read default value: 0000h bit name description 15 - 0 lastdata[15:0] this register stores the data that is just read or written through the spi/uart interface. refer to table-8 and table-9 . 15 14 13 12 11 10 9 8 smallpmod1 5 smallpmod1 4 smallpmod1 3 smallpmod1 2 smallpmod1 1 smallpmod1 0 smallpmod9 smallpmod8 76543210 smallpmod7 smallpmod6 smallpmod5 smallpmod4 smallpmod3 smallpmod2 smallpmod1 smallpmod0 15 14 13 12 11 10 9 8 lastdata15 lastdata14 lastdata13 lastdata12 lastdata11 lastdata10 lastdata9 lastdata8 76543210 lastdata7 lastdata6 lastdata5 lastdata4 las tdata3 lastdata2 lastdata1 lastdata0
26 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 5.3 metering/ measurement calib ration and configuration 5.3.1 metering calibration and configuration register lsb rms/power 16-bit lsb calstart calibration start command address: 08h type: read default value: 0000h bit name description 15 - 0 lsb[15:0] 16-bit lsb of the rms or power registers. note that reading of the l sb[7:0] bits is always 0. address: 20h type: read/write default value: 6886h bit name description 15 - 0 calstart[15:0] metering calibration start command: 6886h: power-on value. metering function is disabled. 5678h: metering calibration startup command. after 56 78h is written to this r egister, registers 21h-2bh resume to their power-on values. the m90e26 star ts to meter and output energy pulses regardless of the correctness of diagnosis. the calerr[1:0] bits ( sysstatus , 01h) are not set and the warnout/ irq pins do not report any warning/interrupt. 8765h: check the correctness of the 21h-2bh registers. if correct, norma l metering. if not correct, meter- ing function is disabled, the calerr[1:0] bits ( sysstatus , 01h) are set and the warnout/irq pins report warning/interrupt. others: metering function is disabled. the calerr[1:0] bits ( sysstatus , 01h) are set and the warnout/irq pins report warning/interrupt. 15 14 13 12 11 10 9 8 lsb15 lsb14 lsb13 lsb12 lsb11 lsb10 lsb0 lsb8 76543210 lsb7 lsb6 lsb5 lsb4 lsb3 lsb2 lsb1 lsb0 15 14 13 12 11 10 9 8 calstart15 calstart14 calstart13 calstart12 calstart11 calstart10 calstart9 calstart8 76543210 calstart7 calstart6 calstart5 calstart4 calstart3 calstart2 calstart1 calstart0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 27 plconsth high word of pl_constant plconstl low word of pl_constant address: 21h type: read/write default value: 0015h bit name description 15 - 0 plcon- sth[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. pl_constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to the meter constant. pl_const ant is a threshold for energy calculated inside the m90e26, i.e., energy lar ger than pl_constant will be accumulated in the corresponding energy registers and then output on cfx. it is suggested to set pl_constant as a multiple of 4 so as to double or redouble meter constant in low current state to save verification time. note: plconsth takes effect af ter plconstl are configured. for details, please refer to related application note 46102. address: 22h type: read/write default value: d174h bit name description 15 - 0 plcon- stl[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. it is suggested to set pl_constant as a multiple of 4. for details, please refer to related application note 46102. 15 14 13 12 11 10 9 8 plconsth15 plconsth14 plconsth13 plconsth12 plconsth11 plconsth10 plconsth9 plconsth8 76543210 plconsth7 plconsth6 plconsth5 plconsth4 p lconsth3 plconsth2 plconsth1 plconsth0 15 14 13 12 11 10 9 8 plconstl15 plconstl14 plconstl13 plconstl12 plconstl11 plconstl10 plconstl9 plconstl8 76543210 plconstl7 plconstl6 plconstl5 plconstl4 p lconstl3 plconstl2 plconstl1 plconstl0
28 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 lgain l line calibration gain lphi l line calibration angle ngain n line calibration gain address: 23h type: read/write default value: 0000h bit name description 15 - 0 lgain[15:0] l line calibration gain. for details, pleas e refer to related application note 46102. address: 24h type: read/write default value: 0000h bit name description 15 - 0 lphi[15:0] l line calibration phase angle. for details, pl ease refer to related application note 46102. address: 25h type: read/write default value: 0000h bit name description 15 - 0 ngain[15:0] n line calibration gain. for details, please refer to related application note 46102. 15 14 13 12 11 10 9 8 lgain15 lgain14 lgain13 lgain12 lgain11 lgain10 lgain9 lgain8 76543210 lgain7 lgain6 lgain5 lgain4 lgain3 lgain2 lgain1 lgain0 15 14 13 12 11 10 9 8 lphi15 - - - - - lphi9 lphi8 76543210 lphi7 lphi6 lphi5 lphi4 lphi3 lphi2 lphi1 lphi0 15 14 13 12 11 10 9 8 ngain15 ngain14 ngain13 ngain12 ngain11 ngain10 ngain9 ngain8 76543210 ngain7 ngain6 ngain5 ngain4 ngain3 ngain2 ngain1 ngain0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 29 nphi n line calibration angle pstartth active startup power threshold pnolth active no-load power threshold address: 26h type: read/write default value: 0000h bit name description 15 - 0 nphi[15:0] n line calibration phase angle. for details, please refer to related application note 46102. address: 27h type: read/write default value: 08bdh bit name description 15 - 0 pstartth[15:0] active startup power threshold. for details, please refer to related application note 46102. address: 28h type: read/write default value: 0000h bit name description 15 - 0 pnolth[15:0] active no-load power threshold. for details, please refer to related application note 46102. 15 14 13 12 11 10 9 8 nphi15 - - - - - nphi9 nphi8 76543210 nphi7 nphi6 nphi5 nphi4 nphi3 nphi2 nphi1 nphi0 15 14 13 12 11 10 9 8 pstartth15 pstartth14 pstartth13 pstartth12 pstartth11 pstartth10 pstartth9 pstartth8 76543210 pstartth7 pstartth6 pstartth5 pstartth4 pstartth3 pstartth2 pstartth1 pstartth0 15 14 13 12 11 10 9 8 pnolth15 pnolth14 pnolth13 pnolth12 pnolth11 pnolth10 pnolth9 pnolth8 76543210 pnolth7 pnolth6 pnolth5 pnolth4 pnolth3 pnolth2 pnolth1 pnolth0
30 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 qstartth reactive startup power threshold qnolth reactive no-load power threshold address: 29h type: read/write default value: 0aech bit name description 15 - 0 qstartth[15:0] reactive startup power threshold. for details , please refer to related application note 46102. address: 2ah type: read/write default value: 0000h bit name description 15 - 0 qnolth[15:0] reactive no-load power threshold. for details, please refer to related application note 46102. 15 14 13 12 11 10 9 8 qstartth15 qstartth14 qstartth13 qstartth12 qstartth11 qstartth10 qstartth9 qstartth8 76543210 qstartth7 qstartth6 qstartth5 qstartth4 qstartth3 qstartth2 qstartth1 qstartth0 15 14 13 12 11 10 9 8 qnolth15 qnolth14 qnolth13 qnolth12 qnolth11 qnolth10 qnolth9 qnolth8 76543210 qnolth7 qnolth6 qnolth5 qnolth4 qnolth3 qnolth2 qnolth1 qnolth0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 31 mmode metering mode configuration address: 2bh type: read/write default value: 9422h bit name description 15 - 13 lgain[2:0] l line current gain, default value is ?100?. 12 - 11 ngain[1:0] n line current gain 00: 2 01: 4 10: 1 (default) 11: 1 10 lnsel this bit specifies metering as l line or n line when metering mode is set to flexible mode by mmd1 and mmd0 pins. 0: n line 1: l line (default) 9 - 8 dishpf[1:0] these bits configure the high filter pass (hpf) after adc. there are two first-order hpf in serial: hpf1 and hpf0. the configuration are applicable to all channels: 7amod cf1 output for active power: 0: forward or reverse energy pulse output (default) 1: absolute energy pulse output 6rmod cf2 output for reactive power: 0: forward (inductive) or reverse (cap acitive) energy puls e output (default) 1: absolute energy pulse output 15 14 13 12 11 10 9 8 lgain2 lgain1 lgain0 ngain1 ngain0 lnsel dishpf1 dishpf0 76543210 amod rmod zxcon1 zxcon0 pthres h3 pthresh2 pthresh1 pthresh0 lgain2 lgain1 lgain0 current channel gain 1xx 1 000 4 001 8 010 16 011 24 dishpf1 dishpf 0 hpf configuration 00 enable hpf1 and hpf0 (default) 0 1 enable hpf1, disable hpf0; 1 0 disable hpf1, enable hpf0; 1 1 disable hpf1 and hpf0
32 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 5 - 4 zxcon[1:0] these bits configure zero-crossing mode. the zx pin outputs 5ms-width high level when voltage crosses zero. 00: positive zero-crossing 01: negative zero-crossing 10: all zero-crossing: both positive and negative zero-crossing (default) 11: no zero-crossing output 3 - 0 pthresh[3:0] these bits configure the l line and n line power difference threshold in anti-tampering mode. pthresh 3 pthresh 2 pthresh 1 pthresh0 threshold 0000 12.5% 0 0 0 1 6.25% 0 0 1 0 3.125% (default) 0 0 1 1 1.5625% 0100 1% 0101 2% 0110 3% 0111 4% 1000 5% 1001 6% 1010 7% 1011 8% 1100 9% 1 1 0 1 10% 1110 11% 1 1 1 1 12%
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 33 cs1 checksum 1 address: 2ch type: read/write default value: 0000h bit name description 15 - 0 cs1[15:0] the cs1 register should be writte n after the 21h-2bh registers are wr itten. suppose the high byte and the low byte of the 21h-2bh registers are shown in below table. the calculation of the cs1 register is as follows: the low byte of 2ch register is: l 2c =mod( h 21 + h 22 +...+ h 2b + l 21 + l 22 +...+ l 2b , 2^8) the high byte of 2ch register is: h 2c = h 21 xor h 22 xor ... xor h 2b xor l 21 xor l 22 xor ... xor l 2b the m90e26 calculates cs1 regularly. if the value of the cs1 register and the calculation by the m90e26 is different when calstart =8765h, the calerr[1:0] bits ( sysstatus , 01h) are set and the warnout and irq pins are asserted. note: the readout value of the cs1 register is the ca lculation by the m90e26, which is different from what is written. 15 14 13 12 11 10 9 8 cs1_15 cs1_14 cs1_13 cs1_12 cs1_11 cs1_10 cs1_9 cs1_8 76543210 cs1_7 cs1_6 cs1_5 cs1_4 cs1_3 cs1_2 cs1_1 cs1_0 register address high byte low byte 21h h 21 l 21 22h h 22 l 22 23h h 23 l 23 24h h 24 l 24 25h h 25 l 25 26h h 26 l 26 27h h 27 l 27 28h h 28 l 28 29h h 29 l 29 2ah h 2a l 2a 2bh h 2b l 2b
34 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 5.3.2 measurement calibration register adjstart measurement calibration start command ugain voltage rms gain address: 30h type: read/write default value: 6886h bit name description 15 - 0 adjstart[15:0] measurement calibration start command 6886h: power-on value. no measurement. 5678h: measurement calibration startup command. after 5678h is written to this register, registers 31h- 3ah resume to their power-on values. the m90e26 starts to measure regardless of the correct- ness of diagnosis. the adjerr[1:0] bits ( sysstatus , 01h) are not set and the irq pin does not report any interrupt. 8765h: check the correctness of the 31h-3ah registers. if correct, normal meas urement. if not correct, measurement function is disabled, the adjerr[1:0] bits ( sysstatus , 01h) are set and the irq pin reports interrupt. others: no measurement. the adjerr[1:0] bits ( sysstatus , 01h) are set and the irq pin reports interrupt. address: 31h type: read/write default value: 6720h bit name description 15 - 0 ugain[15:0] voltage rms gain. for details, please refer to related application note 46102. note: the ugain15 bit should only be '0' 15 14 13 12 11 10 9 8 adjstart15 adjstart14 adjstart13 adjstart12 adjstart11 adjstart10 adjstart9 adjstart8 76543210 adjstart7 adjstart6 adjstart5 adjstart4 adjstart3 adjstart2 adjstart1 adjstart0 15 14 13 12 11 10 9 8 ugain15 ugain14 ugain13 ugain12 ugain11 ugain10 ugain9 ugain8 76543210 ugain7 ugain6 ugain5 ugain4 ugain3 ugain2 ugain1 ugain0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 35 igainl l line current rms gain igainn n line current rms gain uoffset voltage offset address: 32h type: read/write default value: 7a13h bit name description 15 - 0 igainl[15:0] l line current rms gain, for details, please refer to related application note 46102. address: 33h type: read/write default value: 7530h bit name description 15 - 0 igainn[15:0] n line current rms gain. for details, pl ease refer to related application note 46102. address: 34h type: read/write default value: 0000h bit name description 15 - 0 uoffset[15:0] voltage offset. for calculation method, pleas e refer to related application note 46102. 15 14 13 12 11 10 9 8 igainl15 igainl14 igainl13 igainl12 igainl11 igainl10 igainl9 igainl8 76543210 igainl7 igainl6 igainl5 igainl4 igainl3 igainl2 igainl1 igainl0 15 14 13 12 11 10 9 8 igainn15 igainn14 igainn13 igainn12 igainn11 igainn10 igainn9 igainn8 76543210 igainn7 igainn6 igainn5 igainn4 igainn3 igainn2 igainn1 igainn0 15 14 13 12 11 10 9 8 uoffset15 uoffset14 uoffset13 uoffset12 uoffset11 uoffset10 uoffset9 uoffset8 76543210 uoffset7 uoffset6 uoffset5 uoffset4 uoffset3 uoffset2 uoffset1 uoffset0
36 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 ioffsetl l line current offset ioffsetn n line current offset poffsetl l line active power offset address: 35h type: read/write default value: 0000h bit name description 15 - 0 ioffsetl[15:0] l line current offset. for calculation method , please refer to related application note 46102. address: 36h type: read/write default value: 0000h bit name description 15 - 0 ioffsetn[15:0] n line current offset. for calculation method, please refer to related application note 46102. address: 37h type: read/write default value: 0000h bit name description 15 - 0 poffsetl[15:0] l line active power offset. complement, msb is the sign bit. for calculation method, please refer to related application note 46102. 15 14 13 12 11 10 9 8 ioffsetl15 ioffsetl14 ioffsetl13 ioffsetl12 ioffsetl11 ioffsetl10 ioffsetl9 ioffsetl8 76543210 ioffsetl7 ioffsetl6 ioffsetl5 ioffsetl4 ioffsetl3 ioffsetl2 ioffsetl1 ioffsetl0 15 14 13 12 11 10 9 8 ioffsetn15 ioffsetn14 ioffsetn13 ioffsetn12 ioffsetn11 ioffsetn10 ioffsetn9 ioffsetn8 76543210 ioffsetn7 ioffsetn6 ioffsetn5 ioffsetn4 ioffsetn3 ioffsetn2 ioffsetn1 ioffsetn0 15 14 13 12 11 10 9 8 poffsetl15 poffsetl14 poffsetl13 poffsetl12 poffsetl11 poffsetl10 poffsetl9 poffsetl8 76543210 poffsetl7 poffsetl6 poffsetl5 poffsetl4 poffsetl3 poffsetl2 poffsetl1 poffsetl0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 37 qoffsetl l line reactive power offset poffsetn n line active power offset qoffsetn n line reactive power offset address: 38h type: read/write default value: 0000h bit name description 15 - 0 qoffsetl[15:0] l line reactive power offset. complement, msb is the sign bit. for calculation method, please refer to related application note 46102. address: 39h type: read/write default value: 0000h bit name description 15 - 0 poffsetn[15:0] n line active power offset. complement, msb is the sign bit. for calculation method, please refer to related application note 46102. address: 3ah type: read/write default value: 0000h bit name description 15 - 0 qoffsetn[15:0] n line reactive power offset. complement, msb is the sign bit. for calculation met hod, please refer to related application note 46102. 15 14 13 12 11 10 9 8 qoffsetl15 qoffsetl14 qoffsetl13 qoffsetl12 qoffsetl11 qoffsetl10 qoffsetl9 qoffsetl8 76543210 qoffsetl7 qoffsetl6 qoffsetl5 qoffsetl4 qoffsetl3 qoffsetl2 qoffsetl1 qoffsetl0 15 14 13 12 11 10 9 8 poffsetn15 poffsetn14 poffsetn13 poffsetn12 poffsetn11 poffsetn10 poffsetn9 poffsetn8 76543210 poffsetn7 poffsetn6 poffsetn5 poffsetn4 poffsetn3 poffsetn2 poffsetn1 poffsetn0 15 14 13 12 11 10 9 8 qoffsetn15 qoffsetn14 qoffsetn13 qoffsetn12 qoffsetn11 qoffsetn10 qoffsetn9 qoffsetn8 76543210 qoffsetn7 qoffsetn6 qoffsetn5 qoffsetn4 qoffsetn3 qoffsetn2 qoffsetn1 qoffsetn0
38 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 cs2 checksum 2 address: 3bh type: read/write default value: 0000h bit name description 15 - 0 cs2[15:0] the cs2 register should be writte n after the 31h-3ah registers are wr itten. suppose the high byte and the low byte of the 31h-3ah registers are shown in below table. the calculation of the cs2 register is as follows: the low byte of 3bh register is: l 3b =mod( h 31 + h 32 +...+ h 3a + l 31 + l 32 +...+ l 3a , 2^8) the high byte of 3bh register is: h 3b = h 31 xor h 32 xor ... xor h 3a xor l 31 xor l 32 xor ... xor l 3a the m90e26 calculates cs2 regularly. if the value of the cs2 register and the calculation by the m90e26 is different when adjstart =8765h, the adjerr[1:0] bits ( sysstatus , 01h) are set. note: the readout value of the cs2 register is the ca lculation by the m90e26, which is different from what is written. 15 14 13 12 11 10 9 8 cs2_15 cs2_14 cs2_13 cs2_12 cs2_11 cs2_10 cs2_9 cs2_8 76543210 cs2_7 cs2_6 cs2_5 cs2_4 cs2_3 cs2_2 cs2_1 cs2_0 register address high byte low byte 31h h 31 l 31 32h h 32 l 32 33h h 33 l 33 34h h 34 l 34 35h h 35 l 35 36h h 36 l 36 37h h 37 l 37 38h h 38 l 38 39h h 39 l 39 3ah h 3a l 3a
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 39 5.4 energy register theory of energy registers the internal energy resolution is 0.01 pulse. within 0.01 pu lse, forward and reverse energy are counteracted. when energy excee ds 0.01 pulse, the respective forward/reserve energy is increased. the forward and reverse energy are not counteracted in absolute energy registers. take the example of active energy, suppose: t0: forward energy is 12.34 pulses and reverse energy is 1.23 pulses; from t0 to t1: 0.005 forward pulse appeared from t1 to t2: 0.004 reverse pulse appeared from t2 to t3: 0.003 reverse pulse appeared when forward/reverse energy or absolute ener gy reaches 0.1 pulse, the respective regi ster is updated. when forward/reverse ener gy or absolute energy reaches 1 pul se, cfx pins output pulse and the revp/revq bits ( enstatus , 46h) are updated. absolute energy might be more than the sum of forward and reve rse energies. if ?consistency? is required between absolute energ y and forward/reverse energy in system application, absolute e nergy can be obtained by calculating the readout of the forward and rev erse energy registers. apenergy forward active energy t0 t1 t2 t3 forward active pulse 12.34 12.345 12.341 12.34 reserve active pulse 1.23 1.23 1.23 1.232 absolute active pulse 13.57 13.575 13.579 13.582 address: 40h type: read/clear default value: 0000h bit name description 15 - 0 apenergy[15:0] forward active energy; cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maxi mum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 apenergy15 apenergy14 apenergy13 apenergy12 apenergy11 apenergy10 apenergy9 apenergy8 76543210 apenergy7 apenergy6 apenergy5 apenergy4 apenergy3 apenergy2 apenergy1 apenergy0
40 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 anenergy reverse active energy atenergy absolute active energy address: 41h type: read/clear default value: 0000h bit name description 15 - 0 anenergy[15:0] reverse active energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. address: 42h type: read/clear default value: 0000h bit name description 15 - 0 atenergy[15:0] absolute active energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 anenergy15 anenergy14 anenergy13 anenergy12 anenergy11 anenergy10 anenergy9 anenergy8 76543210 anenergy7 anenergy6 anenergy5 anenergy4 a nenergy3 anenergy2 anenergy1 anenergy0 15 14 13 12 11 10 9 8 atenergy15 atenergy14 atenergy13 atenergy12 atenergy11 atenergy10 atenergy9 atenergy8 76543210 atenergy7 atenergy6 atenergy5 atenergy4 atenergy3 atenergy2 atenergy1 atenergy0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 41 rpenergy forward (inductive) reactive energy rnenergy reverse (capacitive) reactive energy address: 43h type: read/clear default value: 0000h bit name description 15 - 0 rpenergy[15:0] forward (inductive) reactive energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. address: 44h type: read/clear default value: 0000h bit name description 15 - 0 rnenergy[15:0] reverse (capacitive) reactive energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maximum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 rpenergy15 rpenergy14 rpenergy13 rpenergy12 rpenergy11 rpenergy10 rpenergy9 rpenergy8 76543210 rpenergy7 rpenergy6 rpenergy5 rpenergy4 r penergy3 rpenergy2 rpenergy1 rpenergy0 15 14 13 12 11 10 9 8 rnenergy15 rnenergy14 rnenergy13 rnenergy12 rnenergy11 rnenergy10 rnenergy9 rnenergy8 76543210 rnenergy7 rnenergy6 rnenergy5 rnenergy4 rnenergy3 rnenergy2 rnenergy1 rnenergy0
42 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 rtenergy absolute reactive energy address: 45h type: read/clear default value: 0000h bit name description 15 - 0 rtenergy[15:0] absolute reactive energy, cleared after read. data format is xxxx.x pulses. resolution is 0.1 pulse. maxi mum is 6553.5 pulses. when the accumulation of this register has achieved ffffh, the continuation accumulation will return to 0000h. 15 14 13 12 11 10 9 8 rtenergy15 rtenergy14 rtenergy13 rtenergy12 rtenergy11 rtenergy10 rtenergy9 rtenergy8 76543210 rtenergy7 rtenergy6 rtenergy5 rtenergy4 r tenergy3 rtenergy2 rtenergy1 rtenergy0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 43 enstatus metering status address: 46h type: read default value after power on: c800h bit name description 15 qnoload this bit indicates whether the m90e26 is in reactive no-load status. 0: not reactive no-load state 1: reactive no-load state 14 pnoload this bit indicates whether th e m90e26 is in active no-load status. 0: not active no-load state 1: active no-load state 13 revq this bit indicates the direction of the last cf2 (reactive output). 0: reactive forward 1: reactive reverse note: this bit is always '0' when the cf2 output is configured to be absolute energy. 12 revp this bit indicates the direction of the last cf1 (active output). 0: active forward 1: active reverse note: this bit is always '0' when the cf1 output is configured to be absolute energy. 11 lline this bit indicates the current metering line in anti-tampering mode. 0: n line 1: l line 10 - 2 - reserved. 1 - 0 lnmode[1:0] these bits indicate the configuration of mmd1 an d mmd0 pins. their relationship is as follows: 15 14 13 12 11 10 9 8 qnoload pnoload revq revp lline - - - 76543210 - - - - - - lnmode1 lnmode0 mmd1 mmd0 lnmod1 lnmod0 l /n metering mode 0000 anti-tampering mode (larger power) 0101 l line mode (fixed l line) 1010 l+n mode (applicable for single-phase three- wire system) 1111 flexible mode (line specified by the lnsel bit ( mmode , 2bh))
44 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 5.5 measurement register irms l line current rms urms voltage rms address: 48h type: read default value: 0000h bit name description 15 - 0 irms[15:0] l line current rms. data format is xx.xxx, which corresponds to 0 ~ 65.535a. for cases when the current exceeds 65.535a, it is su ggested to be handled by mcu in application. for example, the register value can be calibrated to 1/2 of the actual val ue during calibration, then multiplied by 2 in application. address: 49h type: read default value: 0000h bit name description 15 - 0 urms[15:0] voltage rms. data format is xxx.xx, which corresponds to 0 ~ 655.35v. 15 14 13 12 11 10 9 8 irms15 irms14 irms13 irms12 irms11 irms10 irms9 irms8 76543210 irms7 irms6 irms5 irms4 irms3 irms2 irms1 irms0 15 14 13 12 11 10 9 8 urms15 urms14 urms13 urms12 urms11 urms10 urms9 urms8 76543210 urms7 urms6 urms5 urms4 urms3 urms2 urms1 urms0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 45 pmean l line mean active power qmean l line mean reactive power address: 4ah type: read default value: 0000h bit name description 15 - 0 pmean[15:0] l line mean active power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.768kw. if current is specially handle by mcu, the power of the m90e26 and the actual power have the same mul- tiple relationship as the current. address: 4bh type: read default value: 0000h bit name description 15 - 0 qmean[15:0] l line mean reactive power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.768kvar. if current is specially handled by mcu, the power of the m90e26 and the actual power have the same multiple relationship as the current. 15 14 13 12 11 10 9 8 pmean15 pmean14 pmean13 pmean12 pmean11 pmean10 pmean9 pmean8 76543210 pmean7 pmean6 pmean5 pmean4 pmean3 pmean2 pmean1 pmean0 15 14 13 12 11 10 9 8 qmean15 qmean14 qmean13 qmean12 qmean11 qmean10 qmean9 qmean8 76543210 qmean7 qmean6 qmean5 qmean4 qmean3 qmean2 qmean1 qmean0
46 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 freq voltage frequency powerf l line power factor address: 4ch type: read default value: 0000h bit name description 15 - 0 freq[15:0] voltage frequency. data format is xx.xx. frequency measurement range is 45.00~65. 00hz. for example, 1388h corre- sponds to 50.00hz. address: 4dh type: read default value: 0000h bit name description 15 - 0 powerf[15:0] l line power factor. signed, msb is the sign bit. data format is x.xxx. power factor range: -1.000~+1.000. for example, 03e 8h corresponds to the power factor of 1.000, and 83e8h corresponds to the power factor of -1.000. 15 14 13 12 11 10 9 8 freq15 freq14 freq13 freq12 freq11 freq10 freq9 freq8 76543210 freq7 freq6 freq5 freq4 freq3 freq2 freq1 freq0 15 14 13 12 11 10 9 8 powerf15 powerf14 powerf 13 powerf12 powerf11 powerf10 powerf9 powerf8 76543210 powerf7 powerf6 powerf5 powerf4 powerf3 powerf2 powerf1 powerf0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 47 pangle phase angle between voltage and l line current smean l line mean apparent power address: 4eh type: read default value: 0000h bit name description 15 - 0 pangle[15:0] l line voltage current angle. signed, msb is the sign bit. data format is xxx.x. angle range: -180.0~+180.0 degree. address: 4fh type: read default value: 0000h bit name description 15 - 0 smean[15:0] l line mean apparent power. complement, msb is always '0'. data format is xx.xxx, which corresponds to 0~+32.767kva. if current is specially handled by mcu, the power of the m90e26 and the actual power have the same multiple relationship as the current. 15 14 13 12 11 10 9 8 pangle15 pangle14 pangle13 pangle12 pangle11 pangle10 pangle9 pangle8 76543210 pangle7 pangle6 pangle5 pangle4 pangle3 pangle2 pangle1 pangle0 15 14 13 12 11 10 9 8 smean15 smean14 smean13 smean12 smean11 smean10 smean9 smean8 76543210 smean7 smean6 smean5 smean4 smean3 smean2 smean1 smean0
48 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 irms2 n line current rms pmean2 n line mean active power address: 68h type: read default value: 0000h bit name description 15 - 0 irms2[15:0] n line current rms. data format is xx.xxx, wh ich corresponds to 65.535a. for cases when the current exceeds 65.535a, it is su ggested to be handled by mcu in application. for example, the register value can be calibrated to 1/2 of the actual val ue during calibration, then multiplied by 2 in application. address: 6ah type: read default value: 0000h bit name description 15 - 0 pmean2[15:0] n line mean active power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.767kw. if current is specially handled by mcu, the power of the m90e26 and the actual power have the same multiple relationship as the current. 15 14 13 12 11 10 9 8 irms2_15 irms2_14 irms2_13 irms2_12 i rms2_11 irms2_10 irms2_9 irms2_8 76543210 irms2_7 irms2_6 irms2_5 irms2_4 irms2_3 irms2_2 irms2_1 irms2_0 15 14 13 12 11 10 9 8 pmean2_15 pmean2_14 pmean2_13 pmean2_12 pmean2_11 pmean2_10 pmean2_9 pmean2_8 76543210 pmean2_7 pmean2_6 pmean2_5 pmean2_4 pmean2_3 pmean2_2 pmean2_1 pmean2_0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 49 qmean2 n line mean reactive power powerf2 n line power factor address: 6bh type: read default value: 0000h bit name description 15 - 0 qmean2[15:0] n line mean reactive power. complement, msb is the sign bit. data format is xx.xxx, which corresponds to -32.768~+32.767kvar. if current is specially handled by mcu, the power of m90e26 and the actual power have the same multi- ple relationship as the current. address: 6dh type: read default value: 0000h bit name description 15 - 0 powerf2[15:0] n line power factor. signed, msb is the sign bit. data format is x.xxx. power factor range: -1.000~+1.000. for example, 03e 8h corresponds to the power factor of 1.000, an d 83e8h corresponds to the power factor of -1.000. 15 14 13 12 11 10 9 8 qmean2_15 qmean2_14 qmean2_13 qmean2_12 qmean2_11 qmean2_10 qmean2_9 qmean2_8 76543210 qmean2_7 qmean2_6 qmean2_5 qmean2_4 qmean2_3 qmean2_2 qmean2_1 qmean2_0 15 14 13 12 11 10 9 8 powerf2_15 powerf2_14 powerf2_13 powerf2_12 powerf2_11 powerf2_10 powerf2_9 powerf2_8 76543210 powerf2_7 powerf2_6 powerf2_5 powerf2_4 powerf2_3 powerf2_2 powerf2_1 powerf2_0
50 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 pangle2 phase angle between voltage and n line current smean2 n line mean apparent power address: 6eh type: read default value: 0000h bit name description 15 - 0 pangle2[15:0] n line voltage current angle signed, msb is the sign bit. data format is xxx.x. angle range: -180.0~+180.0 degree. address: 6fh type: read default value: 0000h bit name description 15 - 0 smean2[15:0] n line mean apparent power complement, msb is always '0'. data format is xx.xxx, which corresponds to 0~+32.767kva. if current is specially handled by mcu, the power of m90e26 and the actual power have the same multi- ple relationship as the current. 15 14 13 12 11 10 9 8 pangle2_15 pangle2_14 pangle2_13 pangle2_12 pangle2_11 pangle2_10 pangle2_9 pangle2_8 76543210 pangle2_7 pangle2_6 pangle2_5 pangle2_4 pangle2_3 pangle2_2 pangle2_1 pangle2_0 15 14 13 12 11 10 9 8 smean2_15 smean2_14 smean2_13 smean2_12 smean2_11 smean2_10 smean2_9 smean2_8 76543210 smean2_7 smean2_6 smean2_5 smean2_4 smean2_3 smean2_2 smean2_1 smean2_0
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 51 6 electrical specification 6.1 electrical specification parameters and description min. typical max. unit test conditions and comments accuracy dc power supply rejection ratio (psrr) 0.1 % vdd=3.3v 0.3v, 100hz, i=5a, v=220v, l line shunt resistor 150 ? , n line ct 1000:1, sampling resistor 4.8 ac power supply rejection ratio (psrr) 0.1 % vdd=3.3v superimposes 400mvrms, 100hz sinusoidal signal, i=5a, v=220v, l line shunt resistor 150 ? , n line ct 1000:1, sampling resistor 4.8 active energy error (dynamic range 5000:1) 0.1 % l line current gain is ?24?; n line current gain is ?1? measurement error 0.5 % channel characteristics sampling frequency 8 khz harmonic metering (active and reactive) bandwidth 1.1 khz 1% total energy mete ring error limit; v-harmonic <= 10% of fundamental; i-harmonic<=40% of fundamental line frequency 47.5-62.5 hz active energy metering 47.5-52.5 hz reactive energy metering analog input l line current channel differential input 5 25m vrms pga gain is ?24? 7.5 37.5m pga gain is ?16? 15 75m pga gain is ?8? 30 150m pga gain is ?4? 120 600m pga gain is ?1? n line current channel differential input 120 600m vrms dpga gain is ?1? voltage channel differential input 120 600m vrms dpga gain is ?1? l line current channel input impedance 1 k single-ended impedance n line current channel input impedance 400 k single-ended impedance voltage channel input impedance 400 k single-ended impedance l line current channel dc offset 10 mv pga gain is ?24? n line current channel dc offset 10 mv voltage channel dc offset 10 mv reference on-chip reference 1.26 v reference voltage temperature coeffi- cient 15 40 ppm/c clock crystal or external clock 8.192 mhz the accuracy of crystal or external clock is 100 ppm spi/uart interface spi interface bit rate 200 160k bps uart interface baud rate 2400 or 9600 bps baud rate of 2400 and 9600 is automati- cally detected. uart interface tolerance 2%
52 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 pulse width cfx pulse width 80 ms if t 160 ms, width=80ms; if t<160 ms, width = 0.5t. refer to section 6.6 esd charged device model (cdm) 500 v jesd22-c101 human body model (hbm) 2000 v jesd22-a114 latch up 100 ma jesd78a latch up 4.95 v jesd78a operating conditions avdd, analog power supply 2.8 3.3 3.6 v metering precision guaranteed within 3.0v~3.6v. dvdd, digital power supply 2.8 3.3 3.6 v metering precision guaranteed within 3.0v~3.6v. i avdd , analog current 3.4 ma vdd=3.3v, t=25c, vref decoupling capacitor is 1 f. i dvdd , digital current 2.4 ma vdd=3.3v, t=25c, vref decoupling capacitor is 1 f. dc characteristics digital input high level (pin 1, 4, 24, 25, 27 and 28) 2.0 5.5 v vdd=3.3v 10%, digital input high level (pin 9, 12 and 22) 2.0 vdd+0.3 v vdd=3.3v 10% digital input low level 0.8 v vdd=3.3v 10% digital input leakage current 1 a vdd=3.6v, vi=vdd or gnd digital output low level 0.4 v vdd=3.3v, i ol =10ma digital output high level 2.4 v vdd=3.3v, i oh =-10ma digital output low level (osco) 0.4 v vdd=3.3v, i ol =1ma digital output high level (osco) 2.4 v vdd=3.3v, i oh =-1ma
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 53 6.2 spi interface timing the spi interface timing is as shown in figure-10, figure-11 and table-11. figure-10 4-wire spi timing diagram figure-11 3-wire spi timing diagram table-11 spi timing specification symbol description min. typical max. unit t csh note 1 minimum cs high level time 30t note 2 +10 ns t css note 1 cs setup time 3t+10 ns t csd note 1 cs hold time 30t+10 ns t cld note 1 clock disable time 1t ns t clh clock high level time 30t+10 ns t cll clock low level time 16t+10 ns t dis data setup time 3t+10 ns cs sclk sdi sdo t csh t css high impedance high impedance t csd t clh t cll t dis t dih t pd t df valid input valid output t cld t dw sclk sdi sdo high impedance high impedance t clh t cll t dis t dih t pd valid input valid output t dw
54 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 6.3 power on reset timing figure-12 power on reset timing diagram t dih data hold time 22t+10 ns t dw minimum data width 30t+10 ns t pd output delay 14t 15t+20 ns t df note 1 output disable time 16t+20 ns note: 1. not applicable for three-wire spi. 2. t means sclk cycle. t=122ns. (typical value for four-wire spi) table-12 power on reset specification symbol description min. typical max. unit v h power on trigger voltage 2.375 2.5 2.625 v v l power off trigger voltage 2.185 2.3 2.415 v v h -v l hysteretic voltage difference 0.2 v t 1 delay time after power on 5 ms t 2 delay time after power off 10 s table-11 spi timing specification (continued) dvdd reset t 1 v h t 2 v l
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 55 6.4 zero-crossing timing figure-13 zero-crossing timing diagram 6.5 voltage sag timing figure-14 voltage sag timing diagram table-13 zero-crossing specification symbol description min. typical max. unit t zx high level width 5 ms t d delay time 0.5 ms zx (positive zero-crossing) zx (negative zero-crossing) zx (all zero-crossing) t zx t d v voltage sag threshold warnout irq t d v voltage sag threshold
56 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 6.6 pulse output figure-15 output pulse width 6.7 absolute maximum rating table-14 voltage sag specification symbol description min. typical max. unit t d delay time 0.5 ms parameter maximum limit relative voltage between avdd and agnd -0.3v~3.7v relative voltage between dvdd and dgnd -0.3v~3.7v analog input voltage (i1p, i1n, i2p, i2n, vp, vn) -1v~vdd digital input voltage -0.3v~vdd+2.6v operating temperature range -40~85 c maximum junction temperature 150 c package type thermal resistance ja unit condition green ssop28 49 c/w no airflow cfx t p =80ms t p =0.5t t 160ms 10ms t<160ms t p =5ms if t<10ms, force t=10ms
m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 57 ordering information atmel ordering code package carrier temperature range atm90e26-yu-r ssop28 tape&reel industry (-40 c to +85 c ) atm90e26-yu-b ssop28 tube industry (-40 c to +85 c )
58 m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 packaging drawings

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m90e26 [datasheet] atmel-46002b-se-m90e26-datasheet_110714 59 revision history doc. rev. date comments 46002a 4/18/2014 initial document release. 46002b 11/7/2014 removed preliminary.
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